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author | Russ Cox <rsc@swtch.com> | 2011-05-17 18:48:42 -0400 |
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committer | Russ Cox <rsc@swtch.com> | 2011-05-17 18:48:42 -0400 |
commit | af0dea45319aaa8aad011feac472c367165e9020 (patch) | |
tree | 4492de85041e8e52894b3fb47e571a254b4c7d14 /src/libmp/386 | |
parent | 4e247f10fac36e3234aeb6490a66ac57d9520a4a (diff) | |
download | plan9port-af0dea45319aaa8aad011feac472c367165e9020.tar.gz plan9port-af0dea45319aaa8aad011feac472c367165e9020.tar.bz2 plan9port-af0dea45319aaa8aad011feac472c367165e9020.zip |
SunOS fixes (thanks Aram Hăvărneanu)
R=rsc, rsc
http://codereview.appspot.com/4271084
Diffstat (limited to 'src/libmp/386')
-rw-r--r-- | src/libmp/386/mpvecdigmuladd.s | 86 | ||||
-rw-r--r-- | src/libmp/386/mpvecdigmulsub.s | 72 |
2 files changed, 79 insertions, 79 deletions
diff --git a/src/libmp/386/mpvecdigmuladd.s b/src/libmp/386/mpvecdigmuladd.s index ab096461..8c92f61f 100644 --- a/src/libmp/386/mpvecdigmuladd.s +++ b/src/libmp/386/mpvecdigmuladd.s @@ -1,66 +1,66 @@ -/* - * mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p) - * - * p += b*m - * - * each step look like: - * hi,lo = m*b[i] - * lo += oldhi + carry - * hi += carry - * p[i] += lo - * oldhi = hi - * - * the registers are: - * hi = DX - constrained by hardware - * lo = AX - constrained by hardware - * b+n = SI - can't be BP - * p+n = DI - can't be BP - * i-n = BP - * m = BX - * oldhi = CX - * - */ +# +# mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p) +# +# p += b*m +# +# each step look like: +# hi,lo = m*b[i] +# lo += oldhi + carry +# hi += carry +# p[i] += lo +# oldhi = hi +# +# the registers are: +# hi = DX - constrained by hardware +# lo = AX - constrained by hardware +# b+n = SI - can't be BP +# p+n = DI - can't be BP +# i-n = BP +# m = BX +# oldhi = CX +# + .text .p2align 2,0x90 .globl mpvecdigmuladd mpvecdigmuladd: - /* Prelude */ - pushl %ebp /* save on stack */ + # Prelude + pushl %ebp # save on stack pushl %ebx pushl %esi pushl %edi - leal 20(%esp), %ebp /* %ebp = FP for now */ - movl 0(%ebp), %esi /* b */ - movl 4(%ebp), %ecx /* n */ - movl 8(%ebp), %ebx /* m */ - movl 12(%ebp), %edi /* p */ + leal 20(%esp), %ebp # %ebp = FP for now + movl 0(%ebp), %esi # b + movl 4(%ebp), %ecx # n + movl 8(%ebp), %ebx # m + movl 12(%ebp), %edi # p movl %ecx, %ebp - negl %ebp /* BP = -n */ + negl %ebp # BP = -n shll $2, %ecx - addl %ecx, %esi /* SI = b + n */ - addl %ecx, %edi /* DI = p + n */ + addl %ecx, %esi # SI = b + n + addl %ecx, %edi # DI = p + n xorl %ecx, %ecx _muladdloop: - movl (%esi, %ebp, 4), %eax /* lo = b[i] */ - mull %ebx /* hi, lo = b[i] * m */ - addl %ecx,%eax /* lo += oldhi */ + movl (%esi, %ebp, 4), %eax # lo = b[i] + mull %ebx # hi, lo = b[i] * m + addl %ecx,%eax # lo += oldhi jae _muladdnocarry1 - incl %edx /* hi += carry */ + incl %edx # hi += carry _muladdnocarry1: - addl %eax, (%edi, %ebp, 4) /* p[i] += lo */ + addl %eax, (%edi, %ebp, 4) # p[i] += lo jae _muladdnocarry2 - incl %edx /* hi += carry */ + incl %edx # hi += carry _muladdnocarry2: - movl %edx, %ecx /* oldhi = hi */ - incl %ebp /* i++ */ + movl %edx, %ecx # oldhi = hi + incl %ebp # i++ jnz _muladdloop xorl %eax, %eax - addl %ecx, (%edi, %ebp, 4) /* p[n] + oldhi */ - adcl %eax, %eax /* return carry out of p[n] */ + addl %ecx, (%edi, %ebp, 4) # p[n] + oldhi + adcl %eax, %eax # return carry out of p[n] - /* Postlude */ + # Postlude popl %edi popl %esi popl %ebx diff --git a/src/libmp/386/mpvecdigmulsub.s b/src/libmp/386/mpvecdigmulsub.s index 8eec9425..017e86c9 100644 --- a/src/libmp/386/mpvecdigmulsub.s +++ b/src/libmp/386/mpvecdigmulsub.s @@ -1,54 +1,54 @@ -/* - * mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p) - * - * p -= b*m - * - * each step look like: - * hi,lo = m*b[i] - * lo += oldhi + carry - * hi += carry - * p[i] += lo - * oldhi = hi - * - * the registers are: - * hi = DX - constrained by hardware - * lo = AX - constrained by hardware - * b = SI - can't be BP - * p = DI - can't be BP - * i = BP - * n = CX - constrained by LOOP instr - * m = BX - * oldhi = EX - * - */ +# +# mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p) +# +# p -= b*m +# +# each step look like: +# hi,lo = m*b[i] +# lo += oldhi + carry +# hi += carry +# p[i] += lo +# oldhi = hi +# +# the registers are: +# hi = DX - constrained by hardware +# lo = AX - constrained by hardware +# b = SI - can't be BP +# p = DI - can't be BP +# i = BP +# n = CX - constrained by LOOP instr +# m = BX +# oldhi = EX +# + .text .p2align 2,0x90 .globl mpvecdigmulsub mpvecdigmulsub: - /* Prelude */ - pushl %ebp /* save on stack */ + # Prelude + pushl %ebp # save on stack pushl %ebx pushl %esi pushl %edi - leal 20(%esp), %ebp /* %ebp = FP for now */ - movl 0(%ebp), %esi /* b */ - movl 4(%ebp), %ecx /* n */ - movl 8(%ebp), %ebx /* m */ - movl 12(%ebp), %edi /* p */ + leal 20(%esp), %ebp # %ebp = FP for now + movl 0(%ebp), %esi # b + movl 4(%ebp), %ecx # n + movl 8(%ebp), %ebx # m + movl 12(%ebp), %edi # p xorl %ebp, %ebp pushl %ebp _mulsubloop: - movl (%esi, %ebp, 4),%eax /* lo = b[i] */ - mull %ebx /* hi, lo = b[i] * m */ - addl 0(%esp), %eax /* lo += oldhi */ + movl (%esi, %ebp, 4),%eax # lo = b[i] + mull %ebx # hi, lo = b[i] * m + addl 0(%esp), %eax # lo += oldhi jae _mulsubnocarry1 - incl %edx /* hi += carry */ + incl %edx # hi += carry _mulsubnocarry1: subl %eax, (%edi, %ebp, 4) jae _mulsubnocarry2 - incl %edx /* hi += carry */ + incl %edx # hi += carry _mulsubnocarry2: movl %edx, 0(%esp) incl %ebp @@ -61,7 +61,7 @@ _mulsubnocarry2: _mulsubnocarry3: movl $1, %eax done: - /* Postlude */ + # Postlude popl %edi popl %esi popl %ebx |